Thread scheduling is done based on thread behavior and system condition but since the thread behavior is variable at run-time, detection of these changes can have an effective role in improving scheduler decisions. Because shared caches are one of the important resources in multi-core processors, identifying shared cache behavior changes will be effective to improve multi-core scheduling decisions. Therefore, this paper has introduced a phase detection method that classifies the program's intervals based on L2 Miss Count and Perfect IPC. The proposed method dynamically adjusts profiling interval length by using program structure. The goal of authors is that identified phases are valid for different architectures but since L2 Miss Count is architecture-dependent, cache behavior of threads is presented in the form of architectural signature that collected offline. So, the needed information to identify program phases is obtained from architectural signature. The output of the proposed method is phase signature that includes the information about program phases on considered architectures. In the second half of the paper, the accuracy of generated architectural signatures is evaluated and phases of some Splash benchmarks for different architectures are identified then obtained results are compared with actual ones.
|Title of host publication||2011 International Symposium on Performance Evaluation of Computer & Telecommunication Systems|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 15 Aug 2011|