Affinity and coherency aware multi-core scheduling

Reducing the cost of program memory access can improve program performance. In this paper, a scheduling approach based on coherency and thread affinity has been introduced which is able to estimate scheduling cost according to the number of common data blocks and their coherency cost. The estimated results are used to find the appropriate thread mapping to cores so that the number of common data blocks between cores and their coherence cost are reduced. In the proposed model, the effect of shared cache size on affinity and coherency is considered. Since the shared cache behavior on different architectures is not the same and changes according to the cache size, stack distance analysis is used to estimate the behavior of shared cache on different architectures. Finally, the model is evaluated by a synthetic application and SPLASH-2 benchmark.