With the advent of System-On-Chip (SOC) technology, there is a pressing need to enhance the quality of design tools available and increase the level of abstraction at which hardware is designed, implemented and programmed. This would reduce the gap between what is currently achievable technologically, and what hardware engineers are capable to produce given time to market constraints. Hardware development should hence become easier and less time consuming, without scarifying the implementation efficiency. Towards this goal, we present in this paper a simple structural high-level hardware language called HIDE+, particularly suitable for the rapid generation of highly parameterised, and highly efficient, hardware cores. We detail the syntax and semantics of HIDE+ and illustrate how highly scaleable, parameterised and optimised architectures can be described and automatically generated from it, using a small set of constructors. HIDE+ offers a much more abstract way of describing hardware than is possible with traditional hardware description languages such as VHDL or Verilog. Although less abstract and extensive than other electronic system language environments, HIDE+ does not compromise on hardware efficiency. It can thus be of great use to SOC design as an Intellectual Property (IP) development environment.
|Number of pages||9|
|Publication status||Published - 2008|