Hybrid space vector pulse width modulation synthesis to minimize the common-mode voltage

The conventional space vector pulse width modulation (SVPWM) techniques for inverters generate high-frequency common-mode voltage (CMV), which induces high frequency and amplitude shaft voltage. This can exceed the breakdown voltage of the lubricant in the bearings and result in a significant bearing current flowing through the path to the ground. The bearing current causes premature bearing failure and poses electromagnetic interference (EMI) issues, especially in high switching frequency drive systems. In this paper, a hybrid space vector pulse width modulation synthesis (HSVPWMS) is proposed to lower the frequency and amplitude of the CMV. The control algorithm divides each sector in the space vector hexagonal into three segments based on the modulation index and the angle of the reference voltage vector. In each segment, the space vectors that produce minimal CMV are selected to synthesize the reference voltage vector. Both simulation and experimental results have validated the effectiveness of the proposed approach.